1. Field of the Invention
This invention relates to the formation of fuses in an integrated circuit structure. More particularly, this invention relates to the formation of vias or contact openings to an underlying structure, and fuses in the same insulation layer with a minimum of additional steps.
2. Description of the Related Art
In the formation of integrated circuit structures, it is sometimes desirable to provide devices such as programmable read only memory devices (PROMs) in which a fusible link or fuse is provided for each memory cell. Particular fuses to particular memory cells may then be later blown, i.e., during a write sequence, by passing sufficient current through the particular fuse to blow the fuse and thereby sever electrical connection to that particular memory cell.
Such fuses have been constructed either horizontally or vertically in the integrated circuit using conductive material such as metal or metal silicides. Horizontal fuses may be formed, for example, from a patterned layer of conductive material, while vertical fuses may comprise vertical openings in an insulation layer filled with a conductive material, such as a filled via in an insulation layer between two conductive layers or a filled contact opening in an insulation layer between a contact of an active device and a first metal layer.
Usually, however, regardless of the type of material used for the fuse, or its geographical disposition on the integrated circuit structure, i.e. either horizontal or vertical, formation of the fuse or fuses requires a number of additional mask, etching, and deposition steps which all add to the processing time and expense of the process, as well as providing additional steps at which defects or other problems may occur which could adversely impact the yield.
It would, therefore, be highly desirable to provide a process for the construction of fuses in the formation of an integrated circuit structure in which additional processing steps to form the fuses are minimized or eliminated.